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SubjectRe: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache
On 15/07/2022 18:32, Palmer Dabbelt wrote:
> On Wed, 29 Jun 2022 13:07:33 PDT (-0700), wrote:
>> From: Conor Dooley <>
>> The initial PolarFire SoC devicetree must have been forked off from
>> the fu540 one prior to the addition of l2cache controller support being
>> added there. When the controller node was added to mpfs.dtsi, it was
>> not hooked up to the CPUs & thus sysfs reports an incorrect cache
>> configuration. Hook it up.
>> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> I just noticed this as I was looking over the PR I just sent, but since you're sending PRs I'm no longer re-writing your commits and thus I won't be adding stable CCs.  If you want stuff CC'd to stable you'll have to either add it to the tags in the commit, or do so after the fact.

Or option 3, Sasha AUTOSELs it :)

Good point though, I'll make sure to tack on the CC:stable where
needed. I *think* that I have not done this isn't the worst thing
in the world since it is only two patches & only one kernel to
backport it to, but I'll make sure to do it going forward.

Thanks Palmer.
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