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SubjectRe: [PATCH v2 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value
On Wed, 29 Jun 2022 23:35:02 +0200, Martin Blumenstingl wrote:
> The Intel LGM NAND IP only supports two chip selects: There's only two
> CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
> according to the dt-bindings.
>
> Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>

Acked-by: Rob Herring <robh@kernel.org>

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