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SubjectRe: [PATCH 1/4] dt-bindings: misc: tmr-manager: Add device-tree binding for TMR Manager
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On 29/06/2022 13:23, Michal Simek wrote:
>
>
> On 6/29/22 12:07, Krzysztof Kozlowski wrote:
>> On 28/06/2022 07:43, Appana Durga Kedareswara rao wrote:
>>> This commit adds documentation for Triple Modular Redundancy(TMR) Manager
>>> IP. The Triple Modular Redundancy(TMR) Manager is responsible for handling
>>> the TMR subsystem state, including fault detection and error recovery
>>> provides soft error detection, correction and recovery features.
>>>
>>> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
>>> ---
>>> .../bindings/misc/xlnx,tmr-manager.yaml | 48 +++++++++++++++++++
>>
>> This is not a misc device. Find appropriate subsystem for it. It's not
>> EDAC, right?
>
> We were thinking where to put it but it is not EDAC driver.
> If you have better suggestion for subsystem please let us know.

I don't know what's the device about. The description does not help:

"TMR Manager is responsible for TMR subsystem state..."

>
>>
>>> 1 file changed, 48 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
>>> new file mode 100644
>>> index 000000000000..f6cb4d235981
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
>>> @@ -0,0 +1,48 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Xilinx TMR Microblaze Device Tree Bindings
>>
>> s/Device Tree Bindings//
>>
>>> +
>>> +maintainers:
>>> + - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
>>> +
>>> +description: |
>>> + The Triple Modular Redundancy(TMR) Manager is responsible for handling the
>>> + TMR subsystem state, including fault detection and error recovery. The core
>>> + is triplicated in each of the sub-blocks in the TMR subsystem, and provides
>>> + majority voting of its internal state.
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - xlnx,tmr-manager-1.0
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + xlnx,magic1:
>>> + minimum: 0
>>> + maximum: 255
>>> + description:
>>> + Magic number 1, When writing to the control register the first write data
>>> + byte (bits 7:0) must match this value in order to have any effect on the
>>> + nominal recovery function.
>>
>> Register values are usually not in the scope of bindings. We describe
>> here hardware, not programming model, although in case of soft cores
>> maybe it's a bit different.
>
> you need to setup this value for every instance in design tools and it is
> directly present in HW. It means this value is really describing HW.

OK, thanks for clarification.

Best regards,
Krzysztof

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