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Subject[PATCH 12/12] i2c: xiic: Correct the BNB interrupt enable sequence
From: Srinivas Goud <>

With updated AXI IIC IP core(v2.1)there is change in IP behavior
in dynamic mode, where controller initiate read transfer on IIC
bus only after getting the value for the number of bytes to receive.

In the existing xiic_start_recv function Bus Not Busy(BNB)
interrupt is enabled just after "slave address + start"
write to FIFO and before the "count + stop"write to FIFO.
Since IIC controller drives the start address of a transaction
on the bus only after it has received the byte count information
the above sequence can lead to spurious BNB interrupt in case
there is any delay after "slave address + start" write to FIFO.

This is fixed by ensuring that BNB interrupt is enabled only
after "count + stop" has been written to FIFO.

Signed-off-by: Srinivas Goud <>
Signed-off-by: Manikanta Guntupalli <>
drivers/i2c/busses/i2c-xiic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index f29acabba5e7..0a34daa9e372 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -851,13 +851,13 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
i2c_8bit_addr_from_msg(msg) |

- xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
/* If last message, include dynamic stop bit with length */
val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
val |= msg->len;

xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
+ xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
} else {
* If previous message is Tx, make sure that Tx FIFO is empty
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