Messages in this thread |  | | From | Sami Tolvanen <> | Date | Thu, 5 May 2022 09:23:27 -0700 | Subject | Re: [RFC PATCH 09/21] arm64: Add CFI error handling |
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On Thu, May 5, 2022 at 8:45 AM Mark Rutland <mark.rutland@arm.com> wrote: > It would be a bit nicer if we could encode the register index into the BRK > immediate, i.e. allocate a range of 32 immediates (or 31 given BLR XZR is > nonsensical), and have: > > BRK #CFI_BRK_IMM + n > > ... where `n` is the Xn index. > > That way the kernel doesn't need to know the specific code sequence and > wouldn't have to decode the instruction to find the relevant register -- we > could determine that from the ESR alone. That would also avoid tying the > compiler into a specific code sequence, and would allow that to change. > > Since the BRK immediate is 16 bits, we have enough space to also encode the > index of the wB register, which would allow the kernel's BRK handler to recover > and log the expected type value and the the value at the target of the branch > (that latter we can recover from xN, so we don't need wA to be encoded into the > immediate).
Sure, sounds like a good idea.
> ... does the compiler side of that sound possible?
Yes, this should be doable. I'll take a look and change this in the next version.
Sami
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