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SubjectRe: [PATCH v3 8/8] riscv: dts: microchip: add the sundance polarberry
Date
On 04/05/2022 00:55, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Sonntag, 1. Mai 2022, 21:25:59 CEST schrieb Conor Dooley:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add a minimal device tree for the PolarFire SoC based Sundance
>> PolarBerry.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> [...]
>
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> new file mode 100644
>> index 000000000000..96ec589d1571
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> @@ -0,0 +1,95 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>> +
>> +/dts-v1/;
>> +
>> +#include "mpfs.dtsi"
>> +#include "mpfs-polarberry-fabric.dtsi"
>> +
>> +/* Clock frequency (in Hz) of the rtcclk */
>> +#define MTIMER_FREQ 1000000
>> +
>> +/ {
>> + model = "Sundance PolarBerry";
>> + compatible = "sundance,polarberry", "microchip,mpfs";
>> +
>> + aliases {
>> + serial0 = &mmuart0;
>> + ethernet0 = &mac1;
>
> I guess you could sort them alphabetically (ethernet above serial0)
>

I suppose so. I had just matched the order in the icicle but sure.

>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + timebase-frequency = <MTIMER_FREQ>;
>> + };
>> +
>> + ddrc_cache_lo: memory@80000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>> + status = "okay";
>
> "okay" is implied I think, so when you only add the node
> here, you probably don't need to specify the status.
>

Good point.

>> + };
>> +
>> + ddrc_cache_hi: memory@1000000000 {
>> + device_type = "memory";
>> + reg = <0x10 0x00000000 0x0 0xC0000000>;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&refclk {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&mmuart0 {
>> + status = "okay";
>> +};
>> +
>> +&mmc {
>> + status = "okay";
>
> having the status property last (below sd-uhssdr104) can be helpful
> for readability, as readers would know where to expect it.

Ditto

>
>> + bus-width = <4>;
>> + disable-wp;
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + card-detect-delay = <200>;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> +};
>> +
>> +&mac1 {
>> + status = "okay";
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy1>;
>> + phy1: ethernet-phy@5 {
>> + reg = <5>;
>> + ti,fifo-depth = <0x01>;
>> + };
>> + phy0: ethernet-phy@4 {
>> + reg = <4>;
>> + ti,fifo-depth = <0x01>;
>> + };
>> +};
>> +
>> +&mac0 {
>> + status = "disabled";
>
> mac0 is already disabled in the mpfs.dtsi, so you either don't
> need to duplicate it here, or if it's a reminder of something,
> I guess a comment for the "why" would be helpful.

It's a reminder that the SoM does not have a second ethernet
port but the phy is wired up (and usable with the carrier).
I will add a comment.

>
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy0>;
>> +};
>> +
>> +&rtc {
>> + status = "okay";
>> +};
>> +
>> +&mbox {
>> + status = "okay";
>> +};
>> +
>> +&syscontroller {
>> + status = "okay";
>> +};
>
> My personal preference would be alphabetical sorting also for
> phandles, so
>
> &mac0 {}
> &mac1 {}
> &mbox {}
> &refclk {}
> &rtc {}
>
> etc - makes finding things a lot easier in the long run
> especially when files get longer.

Sure, why not.

Thanks for the review,
Conor.

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