lkml.org 
[lkml]   [2022]   [May]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 3/3] PCI: apple: Add support for optional PWREN GPIO
Hi Rob (& Hector),

On 03/05/2022 00.14, Rob Herring wrote:
> On Mon, May 2, 2022 at 4:39 AM Hector Martin <marcan@marcan.st> wrote:
>>
>> WiFi and SD card devices on M1 Macs have a separate power enable GPIO.
>> Add support for this to the PCIe controller. This is modeled after how
>> pcie-fu740 does it.
>
> It did, but it's not ideal really. The problem is the GPIO is really
> associated with the device (WiFi/SD) rather than the PCI host and
> therefore should be part of a WiFi or SD node. You probably don't have
> one (yet), but I would suspect that SD will need one for all the
> standard MMC/SD DT properties.

Not really. The SD card controller is a "standard" GL9755 PCIe SDHC
controller that is already supported by Linux.

It does indeed get a DT node though because the card detect and write
protect signals are inverted and the driver needs to initialize some
PCIe config space registers to compensate for that.

> The secondary issue is we'll end up adding more power sequencing
> properties to control ordering and timing for different devices.

That isn't obvious. Even though there isn't an actual PCIe slot these
still are PCIe compliant devices and therefore governed by the PCIe
standard power up sequencing.

> The exception here is standard PCI slot properties like perst#,
> clkreq, and standard voltage rails can go in the host bridge (and
> for new bindings, those should really be in the root port node). For
> a complicated example, see Hikey960 or 970.

I don't think there is a fundamental difference between having a GPIO
that controls the standard voltage rails of a PCIe slot (like on the
HiFive Unmatched board) and a GPIO that controls the power to a chip
soldered onto the motherboard (like the ASM2824 soldered onto the
HiFive Unmatched board and WiFi/SD on these Apple M1 systems). I
don't think it makes sense to describe this in different ways just
because in one case there is a physical connector present.

Note that the proposed patch does add the "pwren-gpio" property on the
root port node as you suggest.

> Of course with power control related properties there's a chicken or
> egg issue that the PCI device is not discoverable until the device is
> powered on. This issue comes up over and over with various hacky
> solutions in the bindings. The PCI subsystem needs to solve this. My
> suggestion is that if the firmware says there is a device on the bus
> and it wasn't probed, then we should force probing (or add a pre-probe
> hook for drivers). That is what MDIO bus does for example.

But in the case of an actual PCIe slot firmware can't really describe
the PCIe device itself in the DT since it might not be there.

And your suggestion would be quite painful in other contexts where the
device tree will be used (U-Boot, *BSD), which all assume that a PCI
bus can be enumerated.

\
 
 \ /
  Last update: 2022-05-02 23:27    [W:0.021 / U:0.776 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site