lkml.org 
[lkml]   [2022]   [May]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH v1 1/4] soc: imx8mm: gpcv2: Power sequence for DISP
Date
As per the imx8mm reference manual, read bit 25(GPC_DISPMIX_
PWRDNACKN) of the power handshake register and wait for ack during
power on/off.

Signed-off-by: Viraj Shah <viraj.shah@linutronix.de>
---
drivers/soc/imx/gpcv2.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 3cb123016b3e..8ee70c30964f 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -254,11 +254,24 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
+ *
+ * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
+ * Display power on section checks for bit 25 of
+ * Power handshake register to be cleared.
*/
- ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PUP_REQ, reg_val,
- !(reg_val & domain->bits.pxx),
- 0, USEC_PER_MSEC);
+ if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ BIT(7), BIT(7));
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PWRHSK, reg_val,
+ !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
+ 0, USEC_PER_MSEC);
+ } else
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PGC_SW_PUP_REQ, reg_val,
+ !(reg_val & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
goto out_clk_disable;
@@ -355,11 +368,24 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
+ *
+ * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
+ * Display power on section checks for bit 25 of
+ * Power handshake register to be set.
*/
- ret = regmap_read_poll_timeout(domain->regmap,
+ if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
+ regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
+ BIT(7));
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PWRHSK, reg_val,
+ !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
+ 0, USEC_PER_MSEC);
+ } else {
+ ret = regmap_read_poll_timeout(domain->regmap,
GPC_PU_PGC_SW_PDN_REQ, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
+ }
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
goto out_clk_disable;
--
2.20.1
\
 
 \ /
  Last update: 2022-05-02 12:04    [W:0.076 / U:0.040 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site