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    Subject[PATCH 5.10 390/599] clk: qcom: ipq8074: Use floor ops for SDCC1 clock
    From: Dirk Buchwalder <>

    [ Upstream commit b77d8306d84f83d1da68028a68c91da9c867b6f6 ]

    Use floor ops on SDCC1 APPS clock in order to round down selected clock
    frequency and avoid overclocking SD/eMMC cards.

    For example, currently HS200 cards were failling tuning as they were
    actually being clocked at 384MHz instead of 192MHz.
    This caused some boards to disable 1.8V I/O and force the eMMC into the
    standard HS mode (50MHz) and that appeared to work despite the eMMC being
    overclocked to 96Mhz in that case.

    There was a previous commit to use floor ops on SDCC clocks, but it looks
    to have only covered SDCC2 clock.

    Fixes: 9607f6224b39 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks")

    Signed-off-by: Dirk Buchwalder <>
    Signed-off-by: Robert Marko <>
    Reviewed-by: Stephen Boyd <>
    Signed-off-by: Bjorn Andersson <>
    Signed-off-by: Sasha Levin <>
    drivers/clk/qcom/gcc-ipq8074.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
    index b09d99343e09..541016db3c4b 100644
    --- a/drivers/clk/qcom/gcc-ipq8074.c
    +++ b/drivers/clk/qcom/gcc-ipq8074.c
    @@ -1074,7 +1074,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
    .name = "sdcc1_apps_clk_src",
    .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
    .num_parents = 4,
    - .ops = &clk_rcg2_ops,
    + .ops = &clk_rcg2_floor_ops,


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