Messages in this thread |  | | Date | Mon, 4 Apr 2022 03:02:18 +0300 | Subject | Re: [RFC PATCH 3/4] arm64: dts: qcom: sdm845: control RPMHPD performance states with UFS | From | Dmitry Baryshkov <> |
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On 01/04/2022 17:58, Krzysztof Kozlowski wrote: > UFS, when scaling gears, should choose appropriate performance state of > RPMHPD power domain controller. Since UFS belongs to UFS_PHY_GDSC power > domain, add necessary parent power domain to GCC.
This will cause all gcc GDSCs to be rooted in the CX. Are we sure that this is an expected (and correct) change?
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index b31bf62e8680..c999b41c2605 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1078,6 +1078,7 @@ gcc: clock-controller@100000 { > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > + power-domains = <&rpmhpd SDM845_CX>; > }; > > qfprom@784000 { > @@ -2336,8 +2337,22 @@ ufs_mem_hc: ufshc@1d84000 { > <0 0>, > <0 0>, > <0 300000000>; > - > + operating-points-v2 = <&ufs_opp_table>; > status = "disabled"; > + > + ufs_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > ufs_mem_phy: phy@1d87000 {
-- With best wishes Dmitry
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