Messages in this thread Patch in this message |  | | From | Liang Yang <> | Subject | [PATCH v4 2/2] dt-bindings: nand: meson: refine Amlogic NAND controller driver | Date | Sat, 2 Apr 2022 15:49:20 +0800 |
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convert txt to yaml and refine the meson NFC clock document.
Signed-off-by: Liang Yang <liang.yang@amlogic.com> --- .../bindings/mtd/amlogic,meson-nand.txt | 60 -------------- .../bindings/mtd/amlogic,meson-nand.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5794ab1147c1..000000000000 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,60 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. - -Example demonstrate on AXG SoC: - - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - - nand-controller@7800 { - compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; - - clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 000000000000..965a2dd20645 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - "amlogic,meson-gxl-nfc" + - "amlogic,meson-axg-nfc" + + reg: + maxItems: 2 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg-names: + items: + - const: nfc + - const: emmc + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: device + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - reg-names + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-clkc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + nand-controller@7800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "amlogic,meson-axg-nfc"; + reg = <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names = "nfc", "emmc"; + + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; + + }; + }; +... -- 2.34.1
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