Messages in this thread |  | | Date | Sun, 17 Apr 2022 19:41:00 -0700 | Subject | Re: [PATCH v4 2/2] PCI/DPC: Disable DPC service when link is in L2/L3 ready, L2 and L3 state | From | Sathyanarayanan Kuppuswamy <> |
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On 4/8/22 8:31 AM, Kai-Heng Feng wrote: > On Intel Alder Lake platforms, Thunderbolt entering D3cold can cause > some errors reported by AER: > [ 30.100211] pcieport 0000:00:1d.0: AER: Uncorrected (Non-Fatal) error received: 0000:00:1d.0 > [ 30.100251] pcieport 0000:00:1d.0: PCIe Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, (Requester ID) > [ 30.100256] pcieport 0000:00:1d.0: device [8086:7ab0] error status/mask=00100000/00004000 > [ 30.100262] pcieport 0000:00:1d.0: [20] UnsupReq (First) > [ 30.100267] pcieport 0000:00:1d.0: AER: TLP Header: 34000000 08000052 00000000 00000000 > [ 30.100372] thunderbolt 0000:0a:00.0: AER: can't recover (no error_detected callback) > [ 30.100401] xhci_hcd 0000:3e:00.0: AER: can't recover (no error_detected callback) > [ 30.100427] pcieport 0000:00:1d.0: AER: device recovery failed > > Since AER is disabled in previous patch for a Link in L2/L3 Ready, L2 > and L3, also disable DPC here as DPC depends on AER to work. > > Bugzilla:https://bugzilla.kernel.org/show_bug.cgi?id=215453 > Reviewed-by: Mika Westerberg<mika.westerberg@linux.intel.com> > Signed-off-by: Kai-Heng Feng<kai.heng.feng@canonical.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> -- Sathyanarayanan Kuppuswamy Linux Kernel Developer
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