Messages in this thread |  | | Date | Sat, 16 Apr 2022 10:21:54 +0200 | Subject | Re: [PATCH] drm/mipi-dbi: Fix max_chunk calculation in spi_transfer | From | Noralf Trønnes <> |
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Den 08.03.2022 02.56, skrev Yunhao Tian: > In __spi_validate, there's a validation that no partial transfers > are accepted (xfer->len % w_size must be zero). When > max_chunk is not a multiple of bpw (e.g.max_chunk = 65535, > bpw = 16), the transfer will be rejected. > > This patch clamps max_chunk to the word size, preventing
I think align is a better word here than clamp.
> the transfer from being rejected. > > Signed-off-by: Yunhao Tian <t123yh.xyz@gmail.com> > --- > drivers/gpu/drm/drm_mipi_dbi.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > index 71b646c4131f..440dc9fec6cc 100644 > --- a/drivers/gpu/drm/drm_mipi_dbi.c > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > @@ -1182,6 +1182,15 @@ int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, > struct spi_message m; > size_t chunk; > int ret; > + int w_size; > + > + if (bpw <= 8) > + w_size = 1; > + else if (bpw <= 16) > + w_size = 2; > + else > + w_size = 4; > + max_chunk -= (max_chunk % w_size);
mipi_dbi_spi_transfer() is only called with bpw= 8 or 16, so I think this can be simplified to: max_chunk = ALIGN_DOWN(max_chunk, 2); We might shorten the max transfer by one byte when bpw=8, but that doesn't matter. A short comment explaining why we need this would be nice.
Please add a fixes tag so the patch is backported to the stable kernels:
Fixes: d23d4d4dac01 ("drm/tinydrm: Move tinydrm_spi_transfer()")
Noralf.
> > spi_message_init_with_transfers(&m, &tr, 1); >
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