Messages in this thread |  | | Date | Sun, 17 Apr 2022 10:26:22 +0800 | From | Boqun Feng <> | Subject | Re: [PATCH V2 0/3] riscv: atomic: Optimize AMO instructions usage |
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On Sun, Apr 17, 2022 at 12:49:44AM +0800, Guo Ren wrote: [...] > > If both the aq and rl bits are set, the atomic memory operation is > sequentially consistent and cannot be observed to happen before any > earlier memory operations or after any later memory operations in the > same RISC-V hart and to the same address domain. > "0: lr.w %[p], %[c]\n" > " sub %[rc], %[p], %[o]\n" > " bltz %[rc], 1f\n". > - " sc.w.rl %[rc], %[rc], %[c]\n" > + " sc.w.aqrl %[rc], %[rc], %[c]\n" > " bnez %[rc], 0b\n" > - " fence rw, rw\n" > "1:\n" > So .rl + fence rw, rw is over constraints, only using sc.w.aqrl is more proper. >
Can .aqrl order memory accesses before and after it (not against itself, against each other), i.e. act as a full memory barrier? For example, can we end up with u == 1, v == 1, r1 on P0 is 0 and r1 on P1 is 0, for the following litmus test?
C lr-sc-aqrl-pair-vs-full-barrier
{} P0(int *x, int *y, atomic_t *u) { int r0; int r1; WRITE_ONCE(*x, 1); r0 = atomic_cmpxchg(u, 0, 1); r1 = READ_ONCE(*y); } P1(int *x, int *y, atomic_t *v) { int r0; int r1; WRITE_ONCE(*y, 1); r0 = atomic_cmpxchg(v, 0, 1); r1 = READ_ONCE(*x); } exists (u=1 /\ v=1 /\ 0:r1=0 /\ 1:r1=0)
Regards, Boqun [unhandled content-type:application/pgp-signature] |  |