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    Subject[PATCH 5.16 010/186] KVM: arm64: vgic: Read HW interrupt pending state from the HW
    Date
    From: Marc Zyngier <maz@kernel.org>

    [ Upstream commit 5bfa685e62e9ba93c303a9a8db646c7228b9b570 ]

    It appears that a read access to GIC[DR]_I[CS]PENDRn doesn't always
    result in the pending interrupts being accurately reported if they are
    mapped to a HW interrupt. This is particularily visible when acking
    the timer interrupt and reading the GICR_ISPENDR1 register immediately
    after, for example (the interrupt appears as not-pending while it really
    is...).

    This is because a HW interrupt has its 'active and pending state' kept
    in the *physical* distributor, and not in the virtual one, as mandated
    by the spec (this is what allows the direct deactivation). The virtual
    distributor only caries the pending and active *states* (note the
    plural, as these are two independent and non-overlapping states).

    Fix it by reading the HW state back, either from the timer itself or
    from the distributor if necessary.

    Reported-by: Ricardo Koller <ricarkol@google.com>
    Tested-by: Ricardo Koller <ricarkol@google.com>
    Reviewed-by: Ricardo Koller <ricarkol@google.com>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20220208123726.3604198-1-maz@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/kvm/vgic/vgic-mmio.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c
    index 48c6067fc5ecb..f972992682746 100644
    --- a/arch/arm64/kvm/vgic/vgic-mmio.c
    +++ b/arch/arm64/kvm/vgic/vgic-mmio.c
    @@ -248,6 +248,8 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
    IRQCHIP_STATE_PENDING,
    &val);
    WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
    + } else if (vgic_irq_is_mapped_level(irq)) {
    + val = vgic_get_phys_line_level(irq);
    } else {
    val = irq_is_pending(irq);
    }
    --
    2.34.1


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