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Subject[PATCH 3/4] x86/platform/uv: Update TSC sync state for UV5
Date
Update TSC to not check TSC sync state for uv5+ as it is not
available. Therefore it is assumed that TSC will always be in
sync for multiple chassis and will pass the tests for the kernel
to accept it as the clocksource. To disable this check use the
kernel start options tsc=reliable clocksource=tsc.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Steve Wahl <steve.wahl@hpe.com>
---
arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f5a48e66e4f5..387d6533549a 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void)
int mmr_shift;
char *state;

- /* Different returns from different UV BIOS versions */
+ /* UV5+, sync state from bios not available, assumed valid */
+ if (!is_uv(UV2|UV3|UV4)) {
+ pr_debug("UV: TSC sync state for UV5+ assumed valid\n");
+ mark_tsc_async_resets("UV5+");
+ return;
+ }
+
+ /* UV2,3,4, UV BIOS TSC sync state available */
mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
- mmr_shift =
- is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
+ mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;

/* Check if TSC is valid for all sockets */
--
2.26.2
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