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SubjectRe: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
On Mon, 07 Mar 2022 14:30:14 +0000,
Linu Cherian <lcherian@marvell.com> wrote:
>
> When a IAR register read races with a GIC interrupt RELEASE event,
> GIC-CPU interface could wrongly return a valid INTID to the CPU
> for an interrupt that is already released(non activated) instead of 0x3ff.
>
> As a side effect, an interrupt handler could run twice, once with
> interrupt priority and then with idle priority.
>
> As a workaround, gic_read_iar is updated so that it will return a
> valid interrupt ID only if there is a change in the active priority list
> after the IAR read on all the affected Silicons.
>
> Since there are silicon variants where both 23154 and 38545 are applicable,
> workaround for erratum 23154 has been extended to address both of them.
>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
> Changes since V2:
> - Changed masked part number to individual part numbers
> - Added additional comment to clarify on priority groups
>
>
> Changes since V1:
> - IIDR based quirk management done for 23154 has been reverted
> - Extended existing 23154 errata to address 38545 as well,
> so that existing static keys are reused.
> - Added MIDR based support macros to cover all the affected parts
> - Changed the unlikely construct to likely construct in the workaround
> function.
>
>
>
>
> Documentation/arm64/silicon-errata.rst | 2 +-
> arch/arm64/Kconfig | 8 ++++++--
> arch/arm64/include/asm/arch_gicv3.h | 23 +++++++++++++++++++++--
> arch/arm64/include/asm/cputype.h | 13 +++++++++++++
> arch/arm64/kernel/cpu_errata.c | 20 +++++++++++++++++---
> 5 files changed, 58 insertions(+), 8 deletions(-)

Looks good to me this time.

Catalin, Will: happy to take this into the irqchip tree for 5.18 with
your Ack, or you can take it into the arm64 tree with my

Reviewed-by: Marc Zyngier <maz@kernel.org>

Thanks,

M.

--
Without deviation from the norm, progress is not possible.

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