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Subject[PATCH 2/4] dt-bindings: cpufreq: mediatek: add mt8186 cpufreq dt-bindings
Date
1. add cci property.
2. add example of MT8186.

Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
---
.../bindings/cpufreq/cpufreq-mediatek.yaml | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
index 584946eb3790..d3ce17fd8fcf 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
@@ -48,6 +48,10 @@ properties:
When absent, the voltage scaling flow is handled by hardware, hence no
software "voltage tracking" is needed.

+ cci:
+ description:
+ Phandle of the cci to be linked with the phandle of CPU if present.
+
"#cooling-cells":
description:
For details, please refer to
@@ -129,3 +133,40 @@ examples:
/* ... */

};
+
+ - |
+ /* Example 3 (MT8186 SoC) */
+ #include <dt-bindings/clock/mt8186-clk.h>
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp0_00: opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <600000>;
+ opp-level = <15>;
+ required-opps = <&opp2_00>;
+ };
+
+ /* ... */
+
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ sram-supply = <&mt6358_vsram_proc12_reg>;
+ cci = <&cci>;
+ };
+
+ /* ... */
+
+ };
--
2.18.0
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