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SubjectRe: [PATCH] arm64: assembler: Fine-tune code to improve code readability
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On 2022-03-21 02:54, Zhiyuan Dai wrote:
> This patch tweaks the code to improve readability.

...but it also changes what the code actually does :(

> Defined values are:
> PMUVer == 0b0000 : Performance Monitors Extension not implemented.

Plus all the other values, but crucially up to:

"0b1111 IMPLEMENTATION DEFINED form of performance monitors supported,
PMUv3 not supported."

> Signed-off-by: Zhiyuan Dai <daizhiyuan@phytium.com.cn>
> ---
> arch/arm64/include/asm/assembler.h | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index 6ebdc0f..efd43a1 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -489,11 +489,10 @@
> */
> .macro reset_pmuserenr_el0, tmpreg
> mrs \tmpreg, id_aa64dfr0_el1
> - sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4

This extracts a *signed* 4-bit field...

> - cmp \tmpreg, #1 // Skip if no PMU present

...so this rejects values of both 0 and -1.

> - b.lt 9000f
> - msr pmuserenr_el0, xzr // Disable PMU access from EL0
> -9000:
> + ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
> + cbz \tmpreg, .Lskip_pmu_\@ // Skip if no PMU present
> + msr_s SYS_PMUSERENR_EL0, xzr // Disable PMU access from EL0

How confident are you that it's safe to touch a PMUv3 register in an
unknown implementation which explicitly *isn't* PMUv3?

Thanks,
Robin.

> +.Lskip_pmu_\@:
> .endm
>
> /*

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