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Subject[Patch v5 0/4] memory: tegra: Add MC channels and error logging
From tegra186 onward, memory controllers support multiple channels.
Add memory controller channels in device tree and add support to map
address spaces of these channels in tegra MC driver.
When memory controller interrupt occurs, registers from these channels
are required to be read in order to get error information.
Add error logging support from tegra186 onward for memory controller

Ashish Mhetre (4):
memory: tegra: Add memory controller channels support
memory: tegra: Add MC error logging on tegra186 onward
dt-bindings: memory: Update reg maxitems for tegra186
arm64: tegra: Add memory controller channels

Changes in v5:
- Updated patch sequence such that driver patches are before DT patches
- Fixed DT ABI break from v4
- Fixed smatch bug
- Updated description in DT binding documentation
- Updated variable names

Changes in v4:
- Added memory controller channels support
- Added newlines after every break statement of all switch cases
- Fixed compile error with W=1 build
- Fixed the interrupt mask bit logic

Changes in v3:
- Removed unnecessary ifdefs
- Grouped newly added MC registers with existing MC registers
- Removed unnecessary initialization of variables
- Updated code to use newly added field 'has_addr_hi_reg' instead of ifdefs

Changes in v2:
- Updated patch subject and commit message
- Removed separate irq handlers
- Updated tegra30_mc_handle_irq to be used for tegra186 onwards as well

.../nvidia,tegra186-mc.yaml | 16 ++-
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 21 +++-
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 21 +++-
drivers/memory/tegra/mc.c | 114 +++++++++++++++---
drivers/memory/tegra/mc.h | 37 +++++-
drivers/memory/tegra/tegra186.c | 87 +++++++++++++
drivers/memory/tegra/tegra194.c | 44 +++++++
drivers/memory/tegra/tegra234.c | 59 +++++++++
include/soc/tegra/mc.h | 11 ++
10 files changed, 389 insertions(+), 28 deletions(-)


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