lkml.org 
[lkml]   [2022]   [Jan]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v5 12/16] pinctrl: samsung: add FSD SoC specific data
    Date
    Adds Tesla FSD SoC specific data to enable pinctrl.
    FSD SoC has similar pinctrl controller as found in the most
    Samsung/Exynos SoCs.

    Cc: linux-fsd@tesla.com
    Acked-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
    Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
    ---
    .../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +++++++++++++++++++
    drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
    drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
    3 files changed, 74 insertions(+)

    diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
    index 4102ce955bd7..d291819c2f77 100644
    --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
    +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
    @@ -725,3 +725,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
    .ctrl = exynosautov9_pin_ctrl,
    .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
    };
    +
    +/*
    + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
    + * gpio/pin-mux/pinconfig controllers.
    + */
    +
    +/* pin banks of FSD pin-controller 0 (FSYS) */
    +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
    + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
    + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
    + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
    + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
    +};
    +
    +/* pin banks of FSD pin-controller 1 (PERIC) */
    +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
    + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
    + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
    + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
    + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
    + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
    + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
    + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
    +};
    +
    +/* pin banks of FSD pin-controller 2 (PMU) */
    +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
    + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
    +};
    +
    +const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
    + {
    + /* pin-controller instance 0 FSYS0 data */
    + .pin_banks = fsd_pin_banks0,
    + .nr_banks = ARRAY_SIZE(fsd_pin_banks0),
    + .eint_gpio_init = exynos_eint_gpio_init,
    + .suspend = exynos_pinctrl_suspend,
    + .resume = exynos_pinctrl_resume,
    + }, {
    + /* pin-controller instance 1 PERIC data */
    + .pin_banks = fsd_pin_banks1,
    + .nr_banks = ARRAY_SIZE(fsd_pin_banks1),
    + .eint_gpio_init = exynos_eint_gpio_init,
    + .suspend = exynos_pinctrl_suspend,
    + .resume = exynos_pinctrl_resume,
    + }, {
    + /* pin-controller instance 2 PMU data */
    + .pin_banks = fsd_pin_banks2,
    + .nr_banks = ARRAY_SIZE(fsd_pin_banks2),
    + },
    +};
    +
    +const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
    + .ctrl = fsd_pin_ctrl,
    + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
    +};
    diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
    index 568b6e65dfed..f610beab23a0 100644
    --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
    +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
    @@ -1320,6 +1320,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
    .data = &exynos850_of_data },
    { .compatible = "samsung,exynosautov9-pinctrl",
    .data = &exynosautov9_of_data },
    + { .compatible = "tesla,fsd-pinctrl",
    + .data = &fsd_of_data },
    #endif
    #ifdef CONFIG_PINCTRL_S3C64XX
    { .compatible = "samsung,s3c64xx-pinctrl",
    diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
    index 1f8d30ba05af..5b32d3f30fcd 100644
    --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
    +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
    @@ -342,6 +342,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
    extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
    extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
    extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
    +extern const struct samsung_pinctrl_of_match_data fsd_of_data;
    extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
    extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
    extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
    --
    2.25.1
    \
     
     \ /
      Last update: 2022-01-24 15:31    [W:4.531 / U:0.372 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site