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    Subject[PATCH 5.4 297/320] net: axienet: increase default TX ring size to 128
    Date
    From: Robert Hancock <robert.hancock@calian.com>

    commit 2d19c3fd80178160dd505ccd7fed1643831227a5 upstream.

    With previous changes to make the driver handle the TX ring size more
    correctly, the default TX ring size of 64 appears to significantly
    bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
    Increasing this to 128 seems to bring performance up to near line rate and
    shouldn't cause excess bufferbloat (this driver doesn't yet support modern
    byte-based queue management).

    Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
    Signed-off-by: Robert Hancock <robert.hancock@calian.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
    +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
    @@ -41,7 +41,7 @@
    #include "xilinx_axienet.h"

    /* Descriptors defines for Tx and Rx DMA */
    -#define TX_BD_NUM_DEFAULT 64
    +#define TX_BD_NUM_DEFAULT 128
    #define RX_BD_NUM_DEFAULT 1024
    #define TX_BD_NUM_MIN (MAX_SKB_FRAGS + 1)
    #define TX_BD_NUM_MAX 4096

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