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SubjectRE: [PATCH v2] Fixed: Misaligned memory access. Fixed pointer comparison.
Date
From: michael@michaelkloos.com
> Sent: 24 January 2022 19:19

Re-instating the bit I commented on ..
> > ... Additionally, hardware support may not exist and would likely
> > still run slower than aligned accesses even if it did.
>
> > That may not be true.
> > On x86 the cost of misaligned accesses only just measurable.
> > It isn't even one clock per cache line for reads (eg ipcsum).

> I know that the Intel manuals still recommend alignment on x86. I
> haven't tried to measure performance differences yet.

IIRC they recommend aligned writes in particular.
(And don't do misaligned locked accesses that cross page boundaries.)

I've done some measurements for reads and the cost really was minimal.
You'd need to be doing a high proportion of multi-kb misaligned transfers
to cover the cost of any conditional test on aligned tranfsers.

> I think the issue here is that RISC-V is designed as a modular
> architecture. Unlike x86, we don't know that misaligned accesses
> will or will not be supported. I will grant you that if they are
> supported by hardware, it will probably be faster to let the hardware
> natively take care of it. However, if the hardware doesn't support
> it, the kernel won't be compatible with that hardware.

Indeed you really don't want to be fixing up alignment faults - ever.
I've no idea why that ever became acceptable.

David

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