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    Subject[PATCH 5.15 153/846] arm64: dts: ti: k3-j721e: correct cache-sets info
    Date
    From: Peng Fan <peng.fan@nxp.com>

    [ Upstream commit 7a0df1f969c14939f60a7f9a6af72adcc314675f ]

    A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
    - ICache is 3-way set-associative
    - Dcache is 2-way set-associative
    - Line size are 64bytes

    So correct the cache-sets info.

    Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC")
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Reviewed-by: Nishanth Menon <nm@ti.com>
    Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
    Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
    index f0587fde147e6..9f1d25d57a693 100644
    --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
    @@ -61,7 +61,7 @@
    i-cache-sets = <256>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <64>;
    - d-cache-sets = <128>;
    + d-cache-sets = <256>;
    next-level-cache = <&L2_0>;
    };

    @@ -75,7 +75,7 @@
    i-cache-sets = <256>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <64>;
    - d-cache-sets = <128>;
    + d-cache-sets = <256>;
    next-level-cache = <&L2_0>;
    };
    };
    --
    2.34.1


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