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    Subject[PATCH 5.10 127/563] arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
    Date
    From: Nishanth Menon <nm@ti.com>

    [ Upstream commit a172c86931709d6663318609d71a811333bdf4b0 ]

    A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
    - ICache is 3-way set-associative
    - Dcache is 2-way set-associative
    - Line size are 64bytes

    32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways
    512 ways / 2 (Dcache is 2-way per set) = 256 sets.

    So, correct the d-cache-sets info.

    [1] https://www.ti.com/lit/pdf/spruiu1

    Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
    Reported-by: Peng Fan <peng.fan@nxp.com>
    Signed-off-by: Nishanth Menon <nm@ti.com>
    Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
    Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
    Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    index 081b8f3d44c44..03a9623f0f956 100644
    --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
    @@ -60,7 +60,7 @@
    i-cache-sets = <256>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <64>;
    - d-cache-sets = <128>;
    + d-cache-sets = <256>;
    next-level-cache = <&L2_0>;
    };

    @@ -74,7 +74,7 @@
    i-cache-sets = <256>;
    d-cache-size = <0x8000>;
    d-cache-line-size = <64>;
    - d-cache-sets = <128>;
    + d-cache-sets = <256>;
    next-level-cache = <&L2_0>;
    };
    };
    --
    2.34.1


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