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SubjectRe: [v14 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control
Quoting Chun-Jie Chen (2021-07-26 03:57:04)
> In fact, the en_mask is a combination of divider enable mask
> and pll enable bit(bit0).
> Before this patch, we enabled both divider mask and bit0 in prepare(),
> but only cleared the bit0 in unprepare().
> In the future, we hope en_mask will only be used as divider enable mask.
> The enable register(CON0) will be set in 2 steps:
> first is divider mask, and then bit0 during prepare(), and vice versa.
> But considering backward compatibility, at this stage we allow en_mask
> to be a combination or a pure divider enable mask.
> And then we will make en_mask a pure divider enable mask in another
> following patch series.
> Reviewed-by: Ikjoon Jang <>
> Signed-off-by: Weiyi Lu <>
> Signed-off-by: Chun-Jie Chen <>
> ---

Applied to clk-next

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