Messages in this thread |  | | Subject | Re: [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings | From | Sean Anderson <> | Date | Tue, 27 Jul 2021 02:32:30 -0400 |
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On 7/13/21 11:27 AM, Anup Patel wrote: > On Tue, Jul 13, 2021 at 12:52 AM Rob Herring <robh@kernel.org> wrote: >> >> On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: >>> We add DT bindings documentation for the ACLINT MSWI and SSWI >>> devices found on RISC-V SOCs. >>> >>> Signed-off-by: Anup Patel <anup.patel@wdc.com> >>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> >>> --- >>> .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ >>> 1 file changed, 82 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml >>> new file mode 100644 >>> index 000000000000..b74025542866 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml >>> @@ -0,0 +1,82 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: RISC-V ACLINT Software Interrupt Devices >>> + >>> +maintainers: >>> + - Anup Patel <anup.patel@wdc.com> >>> + >>> +description: >>> + RISC-V SOCs include an implementation of the M-level software interrupt >>> + (MSWI) device and the S-level software interrupt (SSWI) device defined >>> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. >>> + >>> + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT >>> + specification located at >>> + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. >>> + >>> + The ACLINT MSWI and SSWI devices directly connect to the M-level and >>> + S-level software interrupt lines of various HARTs (or CPUs) respectively >>> + so the RISC-V per-HART (or per-CPU) local interrupt controller is the >>> + parent interrupt controller for the ACLINT MSWI and SSWI devices. >>> + >>> +allOf: >>> + - $ref: /schemas/interrupt-controller.yaml# >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - riscv,aclint-mswi >>> + - riscv,aclint-sswi >>> + >>> + description: >>> + Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR >>> + "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi". >> >> The schema doesn't match the description. >> >> There's no actual vendor implementation yet? You could do: >> >> items: >> - {} >> - const: riscv,aclint-mswi >> >> But then your example will fail. > > Is it okay to have optional vendor compatible string ?
I think you can express this with something like
properties: compatible: contains: enum: - ...
> > Vendors can add their specific compatible string if there is some > special handling required. If there is not special handling required > then the two compatible strings are enough. > >> >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + "#interrupt-cells": >>> + const: 0 >>> + >>> + interrupts-extended: >>> + minItems: 1 >> >> You need maxItems too. I guess this based on number of cores, so just >> pick a 'should be enough' value. > > There is a limit on the maximum number of connections between the > device and HARTs or CPUs so this will be the maxItems over here. > > I will update this in the next patch revision. > >> >>> + >>> + interrupt-controller: true >>> + >>> +additionalProperties: false >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - interrupts-extended >>> + - interrupt-controller >>> + - "#interrupt-cells" >>> + >>> +examples: >>> + - | >>> + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): >>> + >>> + interrupt-controller@2000000 { >>> + compatible = "riscv,aclint-mswi"; >>> + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; >> >> interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; > > Okay, will update. > >> >>> + reg = <0x2000000 0x4000>; >>> + interrupt-controller; >>> + #interrupt-cells = <0>; >>> + }; >>> + >>> + - | >>> + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): >>> + >>> + interrupt-controller@2100000 { >>> + compatible = "riscv,aclint-sswi"; >>> + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; >> >> Same here. > > Okay, will update here as well. > >> >>> + reg = <0x2100000 0x4000>; >>> + interrupt-controller; >>> + #interrupt-cells = <0>; >>> + }; >>> +... >>> -- >>> 2.25.1 >>> >>> > > Regards, > Anup > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >
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