Messages in this thread |  | | Date | Mon, 26 Jul 2021 09:00:30 +0200 | From | Christoph Hellwig <> | Subject | Re: [RFC 3/5] dma-mapping: Enable global non-coherent pool support for RISC-V |
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On Fri, Jul 23, 2021 at 02:40:29PM -0700, Atish Patra wrote: > Currently, linux,dma-default is used to reserve a global non-coherent pool > to allocate memory for dma operations. This can be useful for RISC-V as > well as the ISA specification doesn't specify a method to modify PMA > attributes or page table entries to define non-cacheable area yet. > A non-cacheable memory window is an alternate options for vendors to > support non-coherent devices.
Please explain why you do not want to use the simply non-cachable window support using arch_dma_set_uncached as used by mips, niops2 and xtensa.
> +static int __dma_init_global_coherent(phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
> { > struct dma_coherent_mem *mem; > > - mem = dma_init_coherent_memory(phys_addr, phys_addr, size, true); > + if (phys_addr == device_addr) > + mem = dma_init_coherent_memory(phys_addr, device_addr, size, true); > + else > + mem = dma_init_coherent_memory(phys_addr, device_addr, size, false);
Nak. The phys_addr != device_addr support is goign away. This needs to be filled in using dma-ranges property hanging of the struct device.
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