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SubjectRe: [PATCH RFC 7/7] kvm: x86: AMX XCR0 support for guest
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On 5/25/2021 5:53 AM, Sean Christopherson wrote:
> On Sun, Feb 07, 2021, Jing Liu wrote:
>> Two XCR0 bits are defined for AMX to support XSAVE mechanism.
>> Bit 17 is for tilecfg and bit 18 is for tiledata.
> This fails to explain why they must be set in tandem.
The spec says,
"executing the XSETBV instruction causes a general-protection fault
(#GP) if ECX=0
and EAX[17] ≠ EAX[18] (XTILECFG and XTILEDATA must be enabled together).
This
implies that the value of XCR0[17:18] is always either 00b or 11b."

I can add more to changelog if this is reasonable.
> Out of curisoity, assuming
> they do indeed need to be set/cleared as a pair, what's the point of having two
> separate bits?
What I can see is to separate different states and mirror by XFD which
can set
bits separately.

Thanks,
Jing

>
>> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
>> ---
>> arch/x86/kvm/x86.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index bfbde877221e..f1c5893dee18 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -189,7 +189,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs;
>> #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
>> | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
>> | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
>> - | XFEATURE_MASK_PKRU)
>> + | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
>>
>> u64 __read_mostly host_efer;
>> EXPORT_SYMBOL_GPL(host_efer);
>> @@ -946,6 +946,12 @@ static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
>> if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
>> return 1;
>> }
>> +
>> + if (xcr0 & XFEATURE_MASK_XTILE) {
>> + if ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)
>> + return 1;
>> + }
>> +
>> vcpu->arch.xcr0 = xcr0;
>>
>> if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
>> --
>> 2.18.4
>>

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