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SubjectRe: [PATCH] riscv: locks: introduce ticket-based spinlock implementation
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On Wed, 24 Mar 2021 05:53:51 PDT (-0700), anup@brainfault.org wrote:
> On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra <peterz@infradead.org> wrote:
>>
>> On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
>> > On Wed, Mar 24, 2021 at 3:45 PM <guoren@kernel.org> wrote:
>> > >
>> > > From: Guo Ren <guoren@linux.alibaba.com>
>> > >
>> > > This patch introduces a ticket lock implementation for riscv, along the
>> > > same lines as the implementation for arch/arm & arch/csky.
>> > >
>> > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
>> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
>> > > Cc: Will Deacon <will.deacon@arm.com>
>> > > Cc: Peter Zijlstra <peterz@infradead.org>
>> > > Cc: Palmer Dabbelt <palmerdabbelt@google.com>
>> > > Cc: Anup Patel <anup@brainfault.org>
>> > > Cc: Arnd Bergmann <arnd@arndb.de>
>> > > ---
>> > > arch/riscv/Kconfig | 1 +
>> > > arch/riscv/include/asm/Kbuild | 1 +
>> > > arch/riscv/include/asm/spinlock.h | 158 ++++++++++++--------------------
>> > > arch/riscv/include/asm/spinlock_types.h | 19 ++--
>> >
>> > NACK from myside.
>> >
>> > Linux ARM64 has moved away from ticket spinlock to qspinlock.
>> >
>> > We should directly go for qspinlock.
>>
>> I think it is a sensible intermediate step, even if you want to go
>> qspinlock. Ticket locks are more or less trivial and get you fairness
>> and all that goodness without the mind bending complexity of qspinlock.
>>
>> Once you have the ticket lock implementation solid (and qrwlock) and
>> everything, *then* start to carefully look at qspinlock.
>
> I do understand qspinlock are relatively complex but the best thing
> about qspinlock is it tries to ensure each CPU spins on it's own location.
>
> Instead of adding ticket spinlock now and later replacing it with qspinlock,
> it is better to straight away explore qspinlock hence my NACK.
>
>>
>> Now, arguably arm64 did the heavy lifting of making qspinlock good on
>> weak architectures, but if you want to do it right, you still have to
>> analyze the whole thing for your own architecture.
>
> Most of the RISC-V implementations are weak memory ordering so it
> makes more sense to explore qspinlock first.

I know I'm somewhat late to the party here. I talked with Will (and
to a lesser extent Peter) about this a week or two ago and it seems the
best way to go here is to start with ticket locks. They're simpler, and
in Arm land they performed better until we got to the larger systems.
Given that we don't have any high performance implementations of the
RISC-V memory model (and likely won't any time soon) it's hard to reason
about the performance of anything like this, but at a bare minimum
having fair locks is a pretty big positive and ticket locks should have
very little overhead while providing fairness.

IMO the decision between ticket and queueing locks is really more of a
property of the hardware/workload than the ISA, though there are of
course some pretty deep ISA dependencies than can make one saner than
the other. It seems best to me to just allow users to pick their own
flavor of locks, and at least PPC is already doing that. I threw
together a quick asm-generic ticket lock that can be selected at compile
time, but I want to spend some more time playing with the other
architectures before sending anything out.

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