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SubjectRe: [PATCH v2 RESEND 5/8] i2c: exynos5: Add bus clock support
On Sat, Dec 04, 2021 at 11:58:17PM +0200, Sam Protsenko wrote:
> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a
> part of USIv2 block, there are two clocks provided to HSI2C controller:
> - PCLK: bus clock (APB), provides access to register interface
> - IPCLK: operating IP-core clock; SCL is derived from this one
> Both clocks have to be asserted for HSI2C to be functional in that case.
> Add code to obtain and enable/disable PCLK in addition to already
> handled operating clock. Make it optional though, as older Exynos SoC
> variants only have one HSI2C clock.
> Signed-off-by: Sam Protsenko <>
> Reviewed-by: Krzysztof Kozlowski <>
> Reviewed-by: Chanho Park <>

This one doesn't apply here? What tree is this based on?

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