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SubjectRe: Re: [PATCH] mips/loongson64: using __fast_iob implement __wbflush() instead of sync
 Hi Jiaxun,

I'm not toward to loongson cpu's barriers, but the semantic of wbflush().

And it is not necessary the safest way:

before applying this patch, wbflush() will be expanded to double __sync(),

if __sync() can empty the uncached store buffer, single one is enough.

After apply this patch, wbflush() will be expanded to a __sync() followed by a __fast_iob();

this is more safe than your's version which blindly copy code from loongson2ef/common/setup.c.

Note, Uncached Accelerated cache mode is only implemented after ls3a2000.

See Mips Run Say:

Most write queues can be emptied out by performing an uncached store to

any location and then performing an operation that reads the same data back.

Put a sync instruction between the write and the read, and that should be effective

on any system compliant with MIPS32/64.

A write queue certainly can't permit the read to overtake the write, it would return stale data.

This is effective, but not necessarily efficient; you can minimize the overhead

by loading from the fastest memory available. Perhaps your system offers

something system-specific but faster.

Again, wbflush is mean to empty data gathered in the uncache store buffers within the CPU.

__wbflush() is only mean to be used internally, wbflush() should be used outside of wbflush.h.

by separate __wbflush out of setup.c, the code is more modularity. it allow you to deselect

CPU_HAS_WB easily and say what will happen.

Actually nothing strange is happen, because uncached accelerated cache mode does not

get used in upstream kernel.

> -----Original Messages-----
&gt; From: "Jiaxun Yang" <>
&gt; Sent Time: 2021-12-04 20:32:37 (Saturday)
&gt; To: suijingfeng <>, "Huacai Chen" <>, "Thomas Bogendoerfer" <>
&gt; Cc: "" <>,
&gt; Subject: Re: [PATCH] mips/loongson64: using __fast_iob implement __wbflush() instead of sync
&gt; Hi Jingfeng,
&gt; I'd suggest you not to mess with barriers on Loongson.
&gt; It's a hell.
&gt; Also Loongson had changed semantics of sync/synci many times.
&gt; They got redefined and swapped. So the present way is just the safest way.
&gt; Thanks.
&gt; - Jiaxun
&gt; 在2021年12月4日十二月 下午12:00,suijingfeng写道:
&gt; &gt; 1) loongson's cpu(ls3a3000, ls3a4000, ls3a5000) have uncache store buffers
&gt; &gt; which is for uncache accleration.
&gt; &gt;
&gt; &gt; Uncached Accelerated is the name under which the R10000 introduced
&gt; &gt; a cache mode that uses the CPU's write buffer to combine writes
&gt; &gt; but that otherwise is uncached.
&gt; &gt;
&gt; &gt; wbflush is mean to empty data gathered in the uncache store buffers
&gt; &gt; within the CPU.
&gt; &gt;
&gt; &gt; 2) The SYNC instruction in R10000
&gt; &gt;
&gt; &gt; A SYNC instruction is not prevented from graduating if the uncached
&gt; &gt; buffer contains any uncached accelerated stores[1].
&gt; &gt;
&gt; &gt; 3) wbflush() implementation of IDT CPU.
&gt; &gt;
&gt; &gt; IDT CPUs enforce strict write priority (all pending writes retired
&gt; &gt; to memory before main memory is read). Thus, implementing wbflush()
&gt; &gt; is as simple as implementing an uncached load.
&gt; &gt;
&gt; &gt; for loongson's cpu, __wbflush should also be implemented with
&gt; &gt; __fast_iob not sync.
&gt; &gt;
&gt; &gt;
&gt; &gt; Signed-off-by: suijingfeng <>
&gt; &gt; ---
&gt; &gt; arch/mips/loongson64/Makefile | 1 +
&gt; &gt; arch/mips/loongson64/setup.c | 17 -----------------
&gt; &gt; arch/mips/loongson64/smp.c | 6 +++---
&gt; &gt; arch/mips/loongson64/wbflush.c | 28 ++++++++++++++++++++++++++++
&gt; &gt; 4 files changed, 32 insertions(+), 20 deletions(-)
&gt; &gt; create mode 100644 arch/mips/loongson64/wbflush.c
&gt; &gt;
&gt; &gt; diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
&gt; &gt; index e806280bbb85..ad00d92c2871 100644
&gt; &gt; --- a/arch/mips/loongson64/Makefile
&gt; &gt; +++ b/arch/mips/loongson64/Makefile
&gt; &gt; @@ -12,3 +12,4 @@ obj-$(CONFIG_SUSPEND) += pm.o
&gt; &gt; obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
&gt; &gt; obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o
&gt; &gt; obj-$(CONFIG_SYSFS) += boardinfo.o
&gt; &gt; +obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
&gt; &gt; diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
&gt; &gt; index 6fe3ffffcaa6..cb10d14da433 100644
&gt; &gt; --- a/arch/mips/loongson64/setup.c
&gt; &gt; +++ b/arch/mips/loongson64/setup.c
&gt; &gt; @@ -3,10 +3,7 @@
&gt; &gt; * Copyright (C) 2007 Lemote Inc. &amp; Institute of Computing Technology
&gt; &gt; * Author: Fuxin Zhang,
&gt; &gt; */
&gt; &gt; -#include <linux export.h="">
&gt; &gt; #include <linux init.h="">
&gt; &gt; -
&gt; &gt; -#include <asm wbflush.h="">
&gt; &gt; #include <asm bootinfo.h="">
&gt; &gt; #include <linux libfdt.h="">
&gt; &gt; #include <linux of_fdt.h="">
&gt; &gt; @@ -17,20 +14,6 @@
&gt; &gt;
&gt; &gt; void *loongson_fdt_blob;
&gt; &gt;
&gt; &gt; -static void wbflush_loongson(void)
&gt; &gt; -{
&gt; &gt; - asm(".set\tpush\n\t"
&gt; &gt; - ".set\tnoreorder\n\t"
&gt; &gt; - ".set mips3\n\t"
&gt; &gt; - "sync\n\t"
&gt; &gt; - "nop\n\t"
&gt; &gt; - ".set\tpop\n\t"
&gt; &gt; - ".set mips0\n\t");
&gt; &gt; -}
&gt; &gt; -
&gt; &gt; -void (*__wbflush)(void) = wbflush_loongson;
&gt; &gt; -EXPORT_SYMBOL(__wbflush);
&gt; &gt; -
&gt; &gt; void __init plat_mem_setup(void)
&gt; &gt; {
&gt; &gt; if (loongson_fdt_blob)
&gt; &gt; diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
&gt; &gt; index 660e1de4412a..0d9f249c95f9 100644
&gt; &gt; --- a/arch/mips/loongson64/smp.c
&gt; &gt; +++ b/arch/mips/loongson64/smp.c
&gt; &gt; @@ -42,13 +42,13 @@ static uint32_t core0_c0count[NR_CPUS];
&gt; &gt; #define loongson3_ipi_write32(action, addr) \
&gt; &gt; do { \
&gt; &gt; writel(action, addr); \
&gt; &gt; - __wbflush(); \
&gt; &gt; + wbflush(); \
&gt; &gt; } while (0)
&gt; &gt; /* write a 64bit value to ipi register */
&gt; &gt; #define loongson3_ipi_write64(action, addr) \
&gt; &gt; do { \
&gt; &gt; writeq(action, addr); \
&gt; &gt; - __wbflush(); \
&gt; &gt; + wbflush(); \
&gt; &gt; } while (0)
&gt; &gt;
&gt; &gt; static u32 (*ipi_read_clear)(int cpu);
&gt; &gt; @@ -418,7 +418,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq,
&gt; &gt; void *dev_id)
&gt; &gt; c0count = c0count ? c0count : 1;
&gt; &gt; for (i = 1; i &lt; nr_cpu_ids; i++)
&gt; &gt; core0_c0count[i] = c0count;
&gt; &gt; - __wbflush(); /* Let others see the result ASAP */
&gt; &gt; + wbflush(); /* Let others see the result ASAP */
&gt; &gt; }
&gt; &gt;
&gt; &gt; return IRQ_HANDLED;
&gt; &gt; diff --git a/arch/mips/loongson64/wbflush.c b/arch/mips/loongson64/wbflush.c
&gt; &gt; new file mode 100644
&gt; &gt; index 000000000000..49f0e4c53196
&gt; &gt; --- /dev/null
&gt; &gt; +++ b/arch/mips/loongson64/wbflush.c
&gt; &gt; @@ -0,0 +1,28 @@
&gt; &gt; +// SPDX-License-Identifier: GPL-2.0-or-later
&gt; &gt; +/*
&gt; &gt; + * This file is subject to the terms and conditions of the GNU General Public
&gt; &gt; + * License. See the file "COPYING" in the main directory of this archive
&gt; &gt; + * for more details.
&gt; &gt; + *
&gt; &gt; + * Copyright (C) 2021
&gt; &gt; + */
&gt; &gt; +#include <linux export.h="">
&gt; &gt; +#include <linux init.h="">
&gt; &gt; +#include <asm wbflush.h="">
&gt; &gt; +#include <asm barrier.h="">
&gt; &gt; +
&gt; &gt; +#ifdef CONFIG_CPU_HAS_WB
&gt; &gt; +
&gt; &gt; +/*
&gt; &gt; + * I/O ASIC systems use a standard writeback buffer that gets flushed
&gt; &gt; + * upon an uncached read.
&gt; &gt; + */
&gt; &gt; +static void wbflush_mips(void)
&gt; &gt; +{
&gt; &gt; + __fast_iob();
&gt; &gt; +}
&gt; &gt; +
&gt; &gt; +void (*__wbflush)(void) = wbflush_mips;
&gt; &gt; +EXPORT_SYMBOL(__wbflush);
&gt; &gt; +
&gt; &gt; +#endif
&gt; &gt; --
&gt; &gt; 2.25.1
&gt; --
&gt; - Jiaxun
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