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Subject[PATCH v3 1/2] EDAC/amd64: Set memory type per DIMM
Date
Current AMD systems allow mixing of DIMM types within a system. However,
DIMMs within a channel, i.e. managed by a single Unified Memory
Controller (UMC), must be of the same type.

Handle this possible configuration by checking and setting the memory
type for each individual EDAC "DIMM" structure.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20211215155309.2711917-2-yazen.ghannam@amd.com

v2->v3:
* Change patch to properly handle systems with different DIMM types.

v1->v2:
* Was patch 3 in v1.
* Update commit message.

drivers/edac/amd64_edac.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index fba609ada0e6..4db92c77276f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1616,19 +1616,23 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
}
}

+static enum mem_type determine_memory_type_df(struct amd64_umc *umc)
+{
+ if (umc->dimm_cfg & BIT(5))
+ return MEM_LRDDR4;
+
+ if (umc->dimm_cfg & BIT(4))
+ return MEM_RDDR4;
+
+ return MEM_DDR4;
+}
+
static void determine_memory_type(struct amd64_pvt *pvt)
{
u32 dram_ctrl, dcsm;

- if (pvt->umc) {
- if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
- pvt->dram_type = MEM_LRDDR4;
- else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
- pvt->dram_type = MEM_RDDR4;
- else
- pvt->dram_type = MEM_DDR4;
+ if (pvt->umc)
return;
- }

switch (pvt->fam) {
case 0xf:
@@ -3547,8 +3551,8 @@ static int init_csrows_df(struct mem_ctl_info *mci)
edac_dbg(1, "MC node: %d, csrow: %d\n",
pvt->mc_node_id, cs);

+ dimm->mtype = determine_memory_type_df(&pvt->umc[umc]);
dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);
- dimm->mtype = pvt->dram_type;
dimm->edac_mode = edac_mode;
dimm->dtype = dev_type;
dimm->grain = 64;
--
2.25.1
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