Messages in this thread |  | | From | Guo Ren <> | Date | Thu, 21 Oct 2021 17:43:05 +0800 | Subject | Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support |
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On Thu, Oct 21, 2021 at 4:33 PM Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 21 Oct 2021 03:00:43 +0100, > Guo Ren <guoren@kernel.org> wrote: > > > > On Wed, Oct 20, 2021 at 11:08 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > On Wed, 20 Oct 2021 15:33:49 +0100, > > > Anup Patel <anup@brainfault.org> wrote: > > > > > > > > On Wed, Oct 20, 2021 at 7:04 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > > > breaks > > > > > > > > > the HW interrupt state or not. > > > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > > > continues irqs could come in. > > > > > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > > > handled? How great... > > > > > > If the completion ID does not match an interrupt source that is > > > > > > currently enabled for the target, the completion is silently ignored. > > > > > > So, C9xx completion depends on enable-bit. > > > > > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > > > can understand that one implementation would be broken, but if the > > > > > PLIC architecture itself is broken, that's far more concerning. > > > > > > > > Yes, we are dealing with a broken/non-compliant PLIC > > > > implementation. > > > > > > > > The RISC-V PLIC spec defines a very different behaviour for the > > > > interrupt claim (i.e. readl(claim)) and interrupt completion (i.e. > > > > writel(claim)). The T-HEAD PLIC implementation does things > > > > different from what the RISC-V PLIC spec says because it will > > > > mask an interrupt upon interrupt claim whereas PLIC spec says > > > > it should only clear the interrupt pending bit (not mask the interrupt). > > > > > > > > Quoting interrupt claim process (chapter 9) from PLIC spec: > > > > "The PLIC can perform an interrupt claim by reading the claim/complete > > > > register, which returns the ID of the highest priority pending interrupt or > > > > zero if there is no pending interrupt. A successful claim will also atomically > > > > clear the corresponding pending bit on the interrupt source." > > > > > > > > Refer, https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > > > That's not the point I'm making. According to Guo, the PLIC (any > > > implementation of it) will ignore a write to claim on a masked > > > interrupt. > > > > > > If that's indeed correct, then a sequence such as: > > > > > > (1) irq = read(claim) > > > (2) mask from the interrupt handler with the right flags so that it > > > isn't done lazily > > > (3) write(irq, claim) > > > > How about letting the IRQ chip change? > > > > diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c > > index a98bcfc4be7b..ed6ace1058ac 100644 > > --- a/kernel/irq/chip.c > > +++ b/kernel/irq/chip.c > > @@ -444,10 +444,10 @@ void unmask_threaded_irq(struct irq_desc *desc) > > { > > struct irq_chip *chip = desc->irq_data.chip; > > > > + unmask_irq(desc); > > + > > if (chip->flags & IRQCHIP_EOI_THREADED) > > chip->irq_eoi(&desc->irq_data); > > - > > - unmask_irq(desc); > > } > > > > /* > > @@ -673,8 +673,8 @@ static void cond_unmask_eoi_irq(struct irq_desc > > *desc, struct irq_chip *chip) > > */ > > if (!irqd_irq_disabled(&desc->irq_data) && > > irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { > > - chip->irq_eoi(&desc->irq_data); > > unmask_irq(desc); > > + chip->irq_eoi(&desc->irq_data); > > } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { > > chip->irq_eoi(&desc->irq_data); > > } > > No, I don't think that's acceptable, and I strongly suspect that other > irqchips have the opposite requirement. You'll have to keep the > workaround in the PLIC code and track the EOI vs unmask to do the > right thing in both callbacks. Okay...
> > M. > > -- > Without deviation from the norm, progress is not possible.
-- Best Regards Guo Ren
ML: https://lore.kernel.org/linux-csky/
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