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SubjectRe: [PATCH] clk: meson: gxbb: Add the spread spectrum bit for MPLL0 on GXBB
Hi Jerome,

On Mon, Oct 18, 2021 at 2:03 PM Jerome Brunet <> wrote:
> > The difference here is BIT(14). un-setting BIT(14) (documented as
> > EN_DDS0) did not change anything according to Christian's test.
> > That also means that SDM, SDM_EN and N2 have the expected values.
> > I manually did the maths:
> > (2000000000Hz * 16384) / ((16384 * 6) + 12808) = 294909640.7Hz
> > which matches what clk_summary sees:
> > 294909641Hz
> ... and (2000000000Hz * 16384) / ((16384 * 6) = 333MHz which is fairly close
> to what you get w/o flipping the bit
This is actually a great hint. So far MPLL clocks have "just worked"
for me and I didn't have to work with this.
With your explanation it makes sense that SDM_EN makes the hardware
use or ignore the SDM value.

> For example yes. I am asking check a bit more what this bit does and
> what it does not:
> - I need confirmation whether or not it does spread spectrum. Yes this
> needs to be observed on a SoC pin, like MCLK with a fairly low divider
> to the averaging effect which could partially mask spread spectrum.
I did some more tests with Christian. It turns out that on GXBB
HHI_MPLL_CNTL7[15] has no impact on the rate seen by meson-clk-msr.
On the other hand, HHI_MPLL_CNTL[25] makes MPLL0 use or ignore the SDM
value (again, verified through meson-clk-msr).

> - Get an idea what it actually does. The 2 calculations above are an
> hint. (Spread spectrum does not change the rate mean value)
My conclusion is that on GXBB:
1) HHI_MPLL_CNTL[25] doesn't control the spread spectrum setting of
MPLL0 - just like you thought
2) HHI_MPLL_CNTL[25] is actually SDM_EN (and HHI_MPLL_CNTL7[15]
doesn't seem to have any impact on MPLL0's output rate)

Please let me know if there's anything else we can test.
Else I'll send a patch for making HHI_MPLL_CNTL[25] the SDM_EN bit of

Best regards,

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