lkml.org 
[lkml]   [2021]   [Oct]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support
On Tue, 19 Oct 2021 14:27:02 +0100,
Guo Ren <guoren@kernel.org> wrote:
>
> On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Tue, 19 Oct 2021 10:33:49 +0100,
> > Guo Ren <guoren@kernel.org> wrote:
> >
> > > > If you have an 'automask' behavior and yet the HW doesn't record this
> > > > in a separate bit, then you need to track this by yourself in the
> > > > irq_eoi() callback instead. I guess that you would skip the write to
> > > > the CLAIM register in this case, though I have no idea whether this
> > > > breaks
> > > > the HW interrupt state or not.
> > > The problem is when enable bit is 0 for that irq_number,
> > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect
> > > the hw state machine. Then this irq would enter in ack state and no
> > > continues irqs could come in.
> >
> > Really? This means that you cannot mask an interrupt while it is being
> > handled? How great...
> If the completion ID does not match an interrupt source that is
> currently enabled for the target, the completion is silently ignored.
> So, C9xx completion depends on enable-bit.

Is that what the PLIC spec says? Or what your implementation does? I
can understand that one implementation would be broken, but if the
PLIC architecture itself is broken, that's far more concerning.

M.

--
Without deviation from the norm, progress is not possible.

\
 
 \ /
  Last update: 2021-10-20 15:34    [W:0.116 / U:3.556 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site