Messages in this thread |  | | Subject | Re: [tip: sched/core] sched: Add cluster scheduler level for x86 | From | Tom Lendacky <> | Date | Wed, 20 Oct 2021 15:51:51 -0500 |
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On 10/20/21 3:40 PM, Peter Zijlstra wrote: > On Wed, Oct 20, 2021 at 10:36:19PM +0200, Peter Zijlstra wrote: > >> OK, I think I see what's happening. >> >> AFAICT cacheinfo.c does *NOT* set l2c_id on AMD/Hygon hardware, this >> means it's set to BAD_APICID. >> >> This then results in match_l2c() to never match. And as a direct >> consequence set_cpu_sibling_map() will generate cpu_l2c_shared_mask with >> just the one CPU set. >> >> And we have the above result and things come unstuck if we assume: >> SMT <= L2 <= LLC >> >> Now, the big question, how to fix this... Does AMD have means of >> actually setting l2c_id or should we fall back to using match_smt() for >> l2c_id == BAD_APICID ? > > The latter looks something like the below and ought to make EPYC at > least function as it did before. > > > --- > arch/x86/kernel/smpboot.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c > index 849159797101..c2671b2333d1 100644 > --- a/arch/x86/kernel/smpboot.c > +++ b/arch/x86/kernel/smpboot.c > @@ -472,7 +472,7 @@ static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) > > /* Do not match if we do not have a valid APICID for cpu: */ > if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) > - return false; > + return match_smt(c, o); /* assume at least SMT shares L2 */ > > /* Do not match if L2 cache id does not match: */ > if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) >
Adding Suravee.
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