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SubjectRe: [PATCH 1/9] clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock
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Il 14/01/21 20:07, Rob Herring ha scritto:
> On Sat, Jan 09, 2021 at 02:46:09PM +0100, AngeloGioacchino Del Regno wrote:
>> This clock enables the GPLL0 output to the multimedia subsystem
>> clock controller.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>> ---
>> drivers/clk/qcom/gcc-msm8998.c | 17 +++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 +
>
> Please put all the dt header changes in their own patch.
>

I thought that this was fine, since I couldn't find *any* patch that is
split like this... at least, if you look at
dt-bindings/clock/qcom,gcc-{msm8974,msm8994,msm8996,msm8998,qcs404,sdm660,sdm845,sm8150}
and qcom,mmcc{apq8084,msm8974,msm8996} ..... and others, at least from
what I can see, nobody has split a code addition requiring that header
update from the actual code.

But if that's a new new new new rule, at this point, I can send a v2 of
this series.

I don't mean to disrespect, nor to be rude in any way but... are you
sure? :))

--Angelo

>> 2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
>> index 9d7016bcd680..d51c556851ca 100644
>> --- a/drivers/clk/qcom/gcc-msm8998.c
>> +++ b/drivers/clk/qcom/gcc-msm8998.c
>> @@ -1341,6 +1341,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
>> },
>> };
>>
>> +static struct clk_branch gcc_mmss_gpll0_clk = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x5200c,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_mmss_gpll0_clk",
>> + .parent_names = (const char *[]){
>> + "gpll0_out_main",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_mss_gpll0_div_clk_src = {
>> .halt_check = BRANCH_HALT_DELAY,
>> .clkr = {
>> @@ -2944,6 +2960,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
>> [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
>> [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
>> [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
>> + [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
>> };
>>
>> static struct gdsc *gcc_msm8998_gdscs[] = {
>> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
>> index 6a73a174f049..47ca17df780b 100644
>> --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
>> +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
>> @@ -184,6 +184,7 @@
>> #define GCC_MSS_MNOC_BIMC_AXI_CLK 175
>> #define GCC_BIMC_GFX_CLK 176
>> #define UFS_UNIPRO_CORE_CLK_SRC 177
>> +#define GCC_MMSS_GPLL0_CLK 178
>>
>> #define PCIE_0_GDSC 0
>> #define UFS_GDSC 1
>> --
>> 2.29.2
>>

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