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SubjectRe: [PATCH v10 2/2] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
On Tue, Dec 29, 2020 at 02:17:09PM +0800, Hector Yuan wrote:
> From: "Hector.Yuan" <hector.yuan@mediatek.com>
>
> Add devicetree bindings for MediaTek HW driver.
>
> Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com>
> ---
> .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 116 ++++++++++++++++++++
> 1 file changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> new file mode 100644
> index 0000000..53e0eb3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> @@ -0,0 +1,116 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek's CPUFREQ Bindings
> +
> +maintainers:
> + - Hector Yuan <hector.yuan@mediatek.com>
> +
> +description:
> + CPUFREQ HW is a hardware engine used by MediaTek
> + SoCs to manage frequency in hardware. It is capable of controlling frequency
> + for multiple clusters.
> +
> +properties:
> + compatible:
> + const: mediatek,cpufreq-hw
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + description: |
> + Addresses and sizes for the memory of the
> + HW bases in each frequency domain.
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: true

This is only correct on common bindings which are incomplete. You need
to define '#performance-domain-cells'.

And this is all dependent on performance-domains binding being accepted.

> +
> +examples:
> + - |
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 0>;
> + reg = <0x000>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 0>;
> + reg = <0x100>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 0>;
> + reg = <0x200>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 0>;
> + reg = <0x300>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 1>;
> + reg = <0x400>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + performance-domains = <&performance 1>;
> + reg = <0x500>;
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75";
> + enable-method = "psci";
> + performance-domains = <&performance 1>;
> + reg = <0x600>;
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75";
> + enable-method = "psci";
> + performance-domains = <&performance 1>;
> + reg = <0x700>;
> + };
> + };
> +
> + /* ... */
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + performance: performance-controller@11bc00 {
> + compatible = "mediatek,cpufreq-hw";
> + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
> + #performance-domain-cells = <1>;
> + };
> + };
> --
> 1.7.9.5
>

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