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SubjectRe: watchdog: sp5100_tco support for AMD V/R/E series
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On 9/7/20 4:20 AM, Jan Kiszka wrote:
> Hi all,
>
> Arsalan reported that the upstream driver for sp5100_tco does not work
> for embedded Ryzen. Meanwhile, I was able to confirm that on an R1505G:
>
> [ 11.607251] sp5100_tco: SP5100/SB800 TCO WatchDog Timer Driver
> [ 11.607337] sp5100-tco sp5100-tco: Using 0xfed80b00 for watchdog MMIO address
> [ 11.607344] sp5100-tco sp5100-tco: Watchdog hardware is disabled
>
> ..and fix it:
>
> diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c
> index 85e9664318c9..5482154fde42 100644
> --- a/drivers/watchdog/sp5100_tco.c
> +++ b/drivers/watchdog/sp5100_tco.c
> @@ -193,7 +193,8 @@ static void tco_timer_enable(struct sp5100_tco *tco)
> /* Set the Watchdog timer resolution to 1 sec and enable */
> sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
> ~EFCH_PM_WATCHDOG_DISABLE,
> - EFCH_PM_DECODEEN_SECOND_RES);
> + EFCH_PM_DECODEEN_SECOND_RES |
> + EFCH_PM_DECODEEN_WDT_TMREN);

Confusing. The register in question is a 32-bit register, but only a byte
is written into it. Bit 24-25 are supposed to be the resolution, bit 25-26
set to 0 enable the watchdog. Bit 7 is supposed to enable MMIO decoding.
This is from AMD Publication 52740. So something in the existing code
is (or seems to be) wrong, but either case I don't see how setting bit 7
(or 31 ?) would enable the watchdog hardware.

Hmm, I wrote that code. Guess I'll need to to spend some time figuring out
what is going on.

Guenter

> break;
> }
> }
>
> Does anyone have an idea if such unconditional setting could be
> problematic on older/different efch? We probe for that bit in
> sp5100_tco_setupdevice but we never set it so far.
>
> I'm missing specs...
>
> Thanks,
> Jan
>

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