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SubjectRe: [PATCH 0/2] iommu/amd: Fix IOMMUv2 devices when SME is active
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Am 07.09.20 um 12:44 schrieb Joerg Roedel:
> On Sun, Sep 06, 2020 at 04:08:58PM +0000, Deucher, Alexander wrote:
>> From f479b9da353c2547c26ebac8930a5dcd9a134eb7 Mon Sep 17 00:00:00 2001
>> From: Alex Deucher <alexander.deucher@amd.com>
>> Date: Sun, 6 Sep 2020 12:05:12 -0400
>> Subject: [PATCH] drm/amdgpu: Fail to load on RAVEN if SME is active
>>
>> Due to hardware bugs, scatter/gather display on raven requires
>> a 1:1 IOMMU mapping, however, SME (System Memory Encryption)
>> requires an indirect IOMMU mapping because the encryption bit
>> is beyond the DMA mask of the chip. As such, the two are
>> incompatible.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 12e16445df7c..d87d37c25329 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -1102,6 +1102,16 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
>> return -ENODEV;
>> }
>>
>> + /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
>> + * however, SME requires an indirect IOMMU mapping because the encryption
>> + * bit is beyond the DMA mask of the chip.
>> + */
>> + if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
>> + dev_info(&pdev->dev,
>> + "SME is not compatible with RAVEN\n");
>> + return -ENOTSUPP;
>> + }
>> +
>> #ifdef CONFIG_DRM_AMDGPU_SI
>> if (!amdgpu_si_support) {
>> switch (flags & AMD_ASIC_MASK) {
>> --
>> 2.25.4
>>
> Looks good to me, thanks.
>
> Acked-by: Joerg Roedel <jroedel@suse.de>

This is really unfortunate, but I don't see any other solution either.

Reviewed-by: Christian König <christian.koenig@amd.com>

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