lkml.org 
[lkml]   [2020]   [Sep]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH v3 02/15] clk: tegra: Don't enable PLLE HW sequencer at init
On Wed, Sep 09, 2020 at 04:10:28PM +0800, JC Kuo wrote:
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
>
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> v3:
> no change
>
> drivers/clk/tegra/clk-pll.c | 12 ------------
> 1 file changed, 12 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>
[unhandled content-type:application/pgp-signature]
\
 
 \ /
  Last update: 2020-09-28 14:53    [W:0.201 / U:3.428 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site