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SubjectRe: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
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On 9/24/20 2:16 AM, Stephen Boyd wrote:
> Quoting Jonathan Marek (2020-09-23 09:10:04)
>> On 9/22/20 3:00 PM, Stephen Boyd wrote:
>>> Quoting Jonathan Marek (2020-09-11 08:34:07)
>>>> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
>>>> new file mode 100644
>>>> index 000000000000..7c0f384a3a42
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/dispcc-sm8250.c
>>>> @@ -0,0 +1,1100 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
>>>> + */
>>>> +
>>> [...]
>>>> +
>>>> +static const struct clk_parent_data disp_cc_parent_data_6[] = {
>>>> + { .fw_name = "bi_tcxo" },
>>>> + { .fw_name = "dsi0_phy_pll_out_dsiclk" },
>>>> + { .fw_name = "dsi1_phy_pll_out_dsiclk" },
>>>
>>> Can we remove clk postfix on these clk names?
>>>
>>
>> This is consistent with the names used in both sdm845 and sc7180
>> drivers. If this should change then those should be changed too?
>
> If DT isn't using it already then it sounds OK to change the other
> SoCs. Otherwise fix it just for this one.
>

Both sdm845 and sc7180 DT are using these names. I kept these names in
the V4 I just sent, keeping things consistent is a lot more beneficial
than dropping 3 extra characters from the DT names.

The sc7180 dispcc driver is recent and has all of these:

- dp_phy_pll_link_clk
- dp_phy_pll_vco_div_clk
- dsi0_phy_pll_out_byteclk
- dsi0_phy_pll_out_dsiclk

So I just can't imagine dropping the clk postfix is actually important.

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