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SubjectRe: [PATCH] PCI: aardvark: Update comment about disabling link training
On Thu, Sep 24, 2020 at 10:46:18AM +0200, Pali Rohár wrote:
> It is not HW bug or workaround for some cards but it is requirement by PCI
> Express spec. After fundamental reset is needed 100ms delay prior enabling
> link training. So update comment in code to reflect this requirement.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> drivers/pci/controller/pci-aardvark.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index 50ab6d7519ae..19b9b79226e5 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -259,7 +259,12 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie)
> if (!pcie->reset_gpio)
> return;
>
> - /* PERST does not work for some cards when link training is enabled */
> + /*
> + * As required by PCI Express spec a delay for at least 100ms after
> + * de-asserting PERST# signal is needed before link training is enabled.
> + * So ensure that link training is disabled prior de-asserting PERST#
> + * signal to fulfill that PCI Express spec requirement.

Can you please include the spec citation here? In the PCIe base spec,
PERST# is only mentioned in PCIe r5.0, sec 6.6.1, and I don't see the
connection there to 100ms between de-assert of PERST# and enabling
link training.

Sec 6.1.1 does talk about 100ms before sending config requests (for
ports that support <= 5 GT/s), and 100ms after link training completes
(for ports that support > 5 GT/s).

Maybe there's more language in a form-factor spec or something?

> + */
> reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
> reg &= ~LINK_TRAINING_EN;
> advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
> --
> 2.20.1
>

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