lkml.org 
[lkml]   [2020]   [Sep]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 1/3] iommu/tegra-smmu: Do not use PAGE_SHIFT and PAGE_MASK
On Fri, Sep 11, 2020 at 12:16:41AM -0700, Nicolin Chen wrote:
> PAGE_SHIFT and PAGE_MASK are defined corresponding to the page size
> for CPU virtual addresses, which means PAGE_SHIFT could be a number
> other than 12, but tegra-smmu maintains fixed 4KB IOVA pages and has
> fixed [21:12] bit range for PTE entries.
>
> So this patch replaces all PAGE_SHIFT/PAGE_MASK references with the
> macros defined with SMMU_PTE_SHIFT.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/iommu/tegra-smmu.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
> index 046add7acb61..789d21c01b77 100644
> --- a/drivers/iommu/tegra-smmu.c
> +++ b/drivers/iommu/tegra-smmu.c
> @@ -130,6 +130,11 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
> #define SMMU_PDE_SHIFT 22
> #define SMMU_PTE_SHIFT 12
>
> +#define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1))
> +#define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK)
> +#define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT)
> +#define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT))
> +
> #define SMMU_PD_READABLE (1 << 31)
> #define SMMU_PD_WRITABLE (1 << 30)
> #define SMMU_PD_NONSECURE (1 << 29)
> @@ -644,7 +649,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
> u32 *pte, dma_addr_t pte_dma, u32 val)
> {
> struct tegra_smmu *smmu = as->smmu;
> - unsigned long offset = offset_in_page(pte);
> + unsigned long offset = SMMU_OFFSET_IN_PAGE(pte);
>
> *pte = val;
>
> @@ -726,7 +731,7 @@ __tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
> pte_attrs |= SMMU_PTE_WRITABLE;
>
> tegra_smmu_set_pte(as, iova, pte, pte_dma,
> - __phys_to_pfn(paddr) | pte_attrs);
> + SMMU_PHYS_PFN(paddr) | pte_attrs);
>
> return 0;
> }
> @@ -790,7 +795,7 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
>
> pfn = *pte & as->smmu->pfn_mask;
>
> - return PFN_PHYS(pfn);
> + return SMMU_PFN_PHYS(pfn);
> }
>
> static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
> @@ -1108,7 +1113,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
> smmu->dev = dev;
> smmu->mc = mc;
>
> - smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
> + smmu->pfn_mask =
> + BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1;

checkpatch no longer warns about lines longer than 80 characters. The
new limit is 100, so you can fit this all on one line.

But either way:

Acked-by: Thierry Reding <treding@nvidia.com>
[unhandled content-type:application/pgp-signature]
\
 
 \ /
  Last update: 2020-09-24 12:24    [W:0.072 / U:4.228 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site