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SubjectRe: [PATCH v2 0/3] SiFive DDR controller and EDAC support
On Mon, Sep 07, 2020 at 11:17:56AM +0530, Yash Shah wrote:
> The series add supports for SiFive DDR controller driver. This driver
> is use to manage the Cadence DDR controller present in SiFive SoCs.
> Currently it manages only the EDAC feature of the DDR controller.
> The series also adds Memory controller EDAC support for SiFive platform.
> It register for notifier event from SiFive DDR controller driver.

This is an odd split and notifiers aren't a great interface. Why not
just combine these? Is there some other DDR controller functionality
planned for the driver?

FYI, highbank_mc_edac.c is also a Cadence controller. IIRC, the register
layout changes for every customer/design.


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