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SubjectRe: [PATCH v3 2/3] dt-bindings: pinctrl: mt8192: add binding document
On Fri, Aug 07, 2020 at 03:49:04PM +0800, Zhiyong Tao wrote:
> The commit adds mt8192 compatible node in binding document.
>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8192.yaml | 149 ++++++++++++++++++
> 1 file changed, 149 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml

Don't set execute permission.

>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
> new file mode 100755
> index 000000000000..3b46bbfa38ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
> @@ -0,0 +1,149 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8192 Pin Controller
> +
> +maintainers:
> + - Sean Wang <sean.wang@mediatek.com>
> +
> +description: |
> + The Mediatek's Pin controller is used to control SoC pins.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8192-pinctrl
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO binding is used,
> + the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> + const: 2
> +
> + gpio-ranges:
> + description: gpio valid number range.
> + maxItems: 1
> +
> + reg:
> + description: |
> + Physical address base for gpio base registers. There are 11 GPIO
> + physical address base in mt8192.
> + maxItems: 11
> +
> + reg-names:
> + description: |
> + Gpio base register names.
> + maxItems: 11
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + description: The interrupt outputs to sysirq.
> + maxItems: 1
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> + '^pins':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, drive strength, input enable/disable and
> + input schmitt.
> + An example of using macro:
> + pincontroller {
> + /* GPIO0 set as multifunction GPIO0 */
> + state_0_node_a {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + };
> + /* GPIO1 set as multifunction PWM */
> + state_0_node_a {
> + pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
> + };
> + };
> + properties:
> + pinmux:
> + $ref: "pinmux-node.yaml"

This is at the wrong level. Should be under '^pins'.

> + description: |
> + Integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are defined
> + as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
> +
> + drive-strength:
> + description: |
> + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
> + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> + bias-pull-down: true
> +
> + bias-pull-up: true
> +
> + bias-disable: true
> +
> + output-high: true
> +
> + output-low: true
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + required:
> + - pinmux
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt8192-pinctrl";
> + reg = <0x10005000 0x1000>,
> + <0x11c20000 0x1000>,
> + <0x11d10000 0x1000>,
> + <0x11d30000 0x1000>,
> + <0x11d40000 0x1000>,
> + <0x11e20000 0x1000>,
> + <0x11e70000 0x1000>,
> + <0x11ea0000 0x1000>,
> + <0x11f20000 0x1000>,
> + <0x11f30000 0x1000>,
> + <0x1000b000 0x1000>;
> + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
> + "iocfg_bl", "iocfg_br", "iocfg_lm",
> + "iocfg_lb", "iocfg_rt", "iocfg_lt",
> + "iocfg_tl", "eint";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 220>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
> + #interrupt-cells = <2>;

Would be good to have a pin node here so you can test you've got the
schema correct.

> + };
> --
> 2.18.0

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