Messages in this thread |  | | Date | Thu, 9 Jul 2020 14:31:11 +0530 | From | Gautham R Shenoy <> | Subject | Re: [PATCH 1/2] powerpc/powernv/idle: Exclude mfspr on HID1,4,5 on P9 and above |
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On Fri, Jul 03, 2020 at 06:16:39PM +0530, Pratik Rajesh Sampat wrote: > POWER9 onwards the support for the registers HID1, HID4, HID5 has been > receded. > Although mfspr on the above registers worked in Power9, In Power10 > simulator is unrecognized. Moving their assignment under the > check for machines lower than Power9 > > Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com>
Nice catch.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> --- > arch/powerpc/platforms/powernv/idle.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c > index 2dd467383a88..19d94d021357 100644 > --- a/arch/powerpc/platforms/powernv/idle.c > +++ b/arch/powerpc/platforms/powernv/idle.c > @@ -73,9 +73,6 @@ static int pnv_save_sprs_for_deep_states(void) > */ > uint64_t lpcr_val = mfspr(SPRN_LPCR); > uint64_t hid0_val = mfspr(SPRN_HID0); > - uint64_t hid1_val = mfspr(SPRN_HID1); > - uint64_t hid4_val = mfspr(SPRN_HID4); > - uint64_t hid5_val = mfspr(SPRN_HID5); > uint64_t hmeer_val = mfspr(SPRN_HMEER); > uint64_t msr_val = MSR_IDLE; > uint64_t psscr_val = pnv_deepest_stop_psscr_val; > @@ -117,6 +114,9 @@ static int pnv_save_sprs_for_deep_states(void) > > /* Only p8 needs to set extra HID regiters */ > if (!cpu_has_feature(CPU_FTR_ARCH_300)) { > + uint64_t hid1_val = mfspr(SPRN_HID1); > + uint64_t hid4_val = mfspr(SPRN_HID4); > + uint64_t hid5_val = mfspr(SPRN_HID5); > > rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); > if (rc != 0) > -- > 2.25.4 > -- Thanks and Regards gautham.
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