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SubjectRe: [PATCH v4 4/4] arm64: dts: marvell: add SMMU support
Date
Tomasz Nowicki <tn@semihalf.com> writes:

> From: Marcin Wojtas <mw@semihalf.com>
>
> Add IOMMU node for Marvell AP806 based SoCs together with platform
> and PCI device Stream ID mapping.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>

Applied on mvebu/dt64

Thanks,

Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-7040.dtsi | 28 +++++++++++++
> arch/arm64/boot/dts/marvell/armada-8040.dtsi | 40 +++++++++++++++++++
> arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 18 +++++++++
> 3 files changed, 86 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> index 47247215770d..7a3198cd7a07 100644
> --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
> @@ -14,3 +14,31 @@
> compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
> "marvell,armada-ap806";
> };
> +
> +&smmu {
> + status = "okay";
> +};
> +
> +&cp0_pcie0 {
> + iommu-map =
> + <0x0 &smmu 0x480 0x20>,
> + <0x100 &smmu 0x4a0 0x20>,
> + <0x200 &smmu 0x4c0 0x20>;
> + iommu-map-mask = <0x031f>;
> +};
> +
> +&cp0_sata0 {
> + iommus = <&smmu 0x444>;
> +};
> +
> +&cp0_sdhci0 {
> + iommus = <&smmu 0x445>;
> +};
> +
> +&cp0_usb3_0 {
> + iommus = <&smmu 0x440>;
> +};
> +
> +&cp0_usb3_1 {
> + iommus = <&smmu 0x441>;
> +};
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> index 7699b19224c2..79e8ce59baa8 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> @@ -15,6 +15,18 @@
> "marvell,armada-ap806";
> };
>
> +&smmu {
> + status = "okay";
> +};
> +
> +&cp0_pcie0 {
> + iommu-map =
> + <0x0 &smmu 0x480 0x20>,
> + <0x100 &smmu 0x4a0 0x20>,
> + <0x200 &smmu 0x4c0 0x20>;
> + iommu-map-mask = <0x031f>;
> +};
> +
> /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
> * in CP master is not connected (by package) to the oscillator. So
> * disable it. However, the RTC clock in CP slave is connected to the
> @@ -23,3 +35,31 @@
> &cp0_rtc {
> status = "disabled";
> };
> +
> +&cp0_sata0 {
> + iommus = <&smmu 0x444>;
> +};
> +
> +&cp0_sdhci0 {
> + iommus = <&smmu 0x445>;
> +};
> +
> +&cp0_usb3_0 {
> + iommus = <&smmu 0x440>;
> +};
> +
> +&cp0_usb3_1 {
> + iommus = <&smmu 0x441>;
> +};
> +
> +&cp1_sata0 {
> + iommus = <&smmu 0x454>;
> +};
> +
> +&cp1_usb3_0 {
> + iommus = <&smmu 0x450>;
> +};
> +
> +&cp1_usb3_1 {
> + iommus = <&smmu 0x451>;
> +};
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> index 7f9b9a647717..12e477f1aeb9 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> @@ -56,6 +56,24 @@
> compatible = "simple-bus";
> ranges = <0x0 0x0 0xf0000000 0x1000000>;
>
> + smmu: iommu@5000000 {
> + compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
> + reg = <0x100000 0x100000>;
> + dma-coherent;
> + #iommu-cells = <1>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@210000 {
> compatible = "arm,gic-400";
> #interrupt-cells = <3>;
> --
> 2.17.1
>

--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

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