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SubjectRe: [PATCH v4 1/5] dt-bindings: phy: Document Samsung UFS PHY bindings
On Fri, Mar 27, 2020 at 10:36:34PM +0530, Alim Akhtar wrote:
> This patch documents Samsung UFS PHY device tree bindings
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> .../bindings/phy/samsung,ufs-phy.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> new file mode 100644
> index 000000000000..41ba481ecc76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0)

Dual license new bindings:

(GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series UFS PHY Device Tree Bindings
> +
> +maintainers:
> + - Alim Akhtar <alim.akhtar@samsung.com>
> +
> +properties:
> + "#phy-cells":
> + const: 0
> +
> + compatible:
> + enum:
> + - samsung,exynos7-ufs-phy
> +
> + reg:
> + maxItems: 1
> + description: PHY base register address
> +
> + reg-names:
> + items:
> + - const: phy-pma
> +
> + clocks:
> + items:
> + - description: PLL reference clock
> + - description: Referencec clock parrent
> +
> + clock-names:
> + items:
> + - const: ref_clk_parent
> + - const: ref_clk

Doesn't match what 'clocks' says.

Also, why do you need the parent in DT? Just use clk_get_parent(). DT
should reflect actual h/w clock connections (not what the driver
happens to need). Also, there's the assigned-clocks binding.

> +
> + samsung,pmu-syscon:
> + $ref: '/schemas/types.yaml#/definitions/phandle'
> + description: phandle for PMU system controller interface, used to
> + control pmu registers for power isolation

We have a binding for power domains. Use that for power isolation.

> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - samsung,pmu-syscon
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/exynos7-clk.h>
> +
> + ufs_phy: ufs-phy@15571800 {
> + compatible = "samsung,exynos7-ufs-phy";
> + reg = <0x15571800 0x240>;
> + reg-names = "phy-pma";
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #phy-cells = <0>;
> + clocks = <&clock_fsys1 MOUT_FSYS1_PHYCLK_SEL1>,
> + <&clock_top1 CLK_SCLK_PHY_FSYS1_26M>;
> + clock-names = "ref_clk_parent",
> + "ref_clk";
> + };
> +...
>
> base-commit: fb33c6510d5595144d585aa194d377cf74d31911
> --
> 2.17.1
>

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